1. Field of the Invention
This invention relates generally to a non-volatile semiconductor memory device, and in particular to a non-volatile semiconductor memory device capable of high speed read-out operation.
2. Description of the Prior Art
One typical non-volatile semiconductor memory device is an electrically erasable programmable read only memory or EEPROM and its overall arrangement is illustrated in the block diagram of FIG. 1.
Referring to FIG. 1, the EEPROM includes a memory array 50 formed of a plurality of EEPROM cells, a row address buffer 51 and a column address buffer 52 which receive externally applied row address signals and externally applied column address signals, respectively. The EEPROM also includes a row decoder 53 and a column decoder 54. The row decoder 53 decodes the address output from the row address buffer 51 and activates a word line coupled to a particular memory cell to be selected in the memory array while the column decoder 54 decodes the address output from the column address buffer 52 to activate a Y gate to connect a bit line coupled to the particular memory cell to I/O line. A sense amplifier 56 senses via a Y gate 55 a data signal stored in the memory cell which has been selected by the row and column decoders. The sensed signal is amplified in the sense amplifier and fed out through an output buffer 57. Included also in the EEPROM is an input buffer 58 for providing control signals to various circuits associated with the memory array.
In FIG. 2, there is shown a schematic circuit diagram of the memory array and Y gate of FIG. 1.
Referring to FIG. 2, the Y gate 55 comprises a transistor 8 connected between an I/O line 10 and a bit line 6, and a transistor 9 connected between the CG line 11 and a control gate line 5. To the gates of these transistors 8 and 9, a Y gate signal Y2 is supplied. A similar transistor arrangement is provided for a Y gate signal Y1.
In the configuration of the memory cell array of FIG. 2, only four memory cells are shown for storing four bits of data. Each memory cell comprises a memory transistor 3 having a floating gate, and a select transistor 2 for transferring a data signal stored in the memory transistor 3 to a bit line 6. The gate of the select transistor 2 is coupled to a word line 1. Another select transistor 4 is provided to transfer a signal on the control gate line to the gate of the memory transistor 3. The gate of the select transistor 4 is coupled to the word line 1.
To briefly describe the operation, the memory transistor 3 is capable of taking two different storage or logic states depending on whether electrons are accumulated on its floating gate. When electrons are injected into the floating gate of the transistor 3, the threshold voltage of the transistor shifts high, and therefore the transistor is non-conductive during read-out operation. This condition is defined as a logic "1" state. On the other hand, when electrons are removed from the floating gate, the threshold voltage of transistor 3 shifts low, and the transistor 3 is conducting during the read-out operation. This condition is defined as a logic "0" state.
The sense amplifier provides a read-out voltage to the bit line 6 via the transistor 8. From the bit line 6, the read-out voltage is fed to the memory transistor 3 through the transistor 2. This enables the sense amplifier to detect whether the current flows through the transistor 3 or not, that is, to read the stored data of the memory transistor 3.
FIG. 3 schematically illustrate one prior art sense amplifier which is disclosed in Japanese Laying-Open Gazette No. 170097/1987.
The sense amplifier 56 of FIG. 3 includes a current-to-voltage converter circuit 56a for performing a current to voltage conversion of the data stored in the memory cell, and an inverter circuit 56b for inverting the output of the converter circuit. The current-to-voltage converter 56a comprises P-channel MOS transistors 15 and 18, and N-channel MOS transistors 16, 17 and 19.
Now the operation of the sense amplifier 56 is briefly described in conjunction with a memory cell transistor 30a of an EPROM, but it operates much the same way in connection with a memory cell of the EEPROM.
In read-out operation, when the transistor 3a is in a logic state to render it conductive, a node N1 is brought to about 1.0 V. As a result, a transistor 16 is moderately or slightly turned on, bringing a node N2 to about 2 V. Then, the transistors 17 and 19 turn on slightly, but a node N3 is brought only to about the same voltage level as the node N1 (i.e. 1.0 V) because the on resistance of the transistor 18 is preselected much higher than that of the transistor 19.
When the transistor 3a is in a logic state to render it non-conductive during the read-out operation, the bit line 16 is charged by a supply voltage Vcc applied thereto through the transistor 18, and the node N1 is brought to about 1.1 V. This also brings the node N2 to about 1.8 V, and the voltage between the gate and source of the transistors 17 and 19 to about 0.7 V. Thus, the transistors 17 and 19 are turned off, and the node N3 is brought up to 5 V.
With the configurations of the prior art EEPROM and EPROM as briefly stated above, as the density of the memory devices increases, the current flow through individual memory cell or the cell current decreases accordingly because of the reduction of the memory cell size. In order for the sense amplifier to detect the small cell current, it is necessary to reduce the sizes of the load transistors in the sense amplifier, for example, the transistor 18. The small size transistor 18 inevitably retards the charging of the bit line by the supply voltage Vcc, which, in turn, increases the time needed to read out the data stored in the memory cell.
FIG. 4 schematically illustrates a prior art flash EEPROM disclosed in a paper entitled "A 256k Flash EEPROM using Triple Polysilicon Technology" by F. Masuoka et al. which was presented in an ISSCC held Feb. 14, 1985.
Referring to FIG. 4, the flash EEPROM includes a plurality of reference cells in addition to the ordinary memory cells. A data stored in the memory cell and a signal from the reference cell are, after undergoing the current to voltage conversion, supplied to a differential amplifier for sensing the data stored in the selected memory cell. A major disadvantage of this type of EEPROM sensing scheme is that it is necessary to provide additional cells for the reference purpose and that it is extremely difficult to preset the threshold voltage or cell current of these reference cells.
In FIG. 5, there is shown a circuit diagram of a prior art read-only memory (or ROM) disclosed in Japanese Laying-Open Gazette No. 151392/1984.
Referring to FIG. 5, the ROM has a memory array divided into two sections (not shown). When a particular memory cell in one array section is selected, the other array section not including the selected memory cell provides a reference voltage. The reference voltage and a voltage from the selected memory cell are differentially amplified by the differential amplifier. This ROM differs in configuration from the ROM of this invention to be described below in that it does not includes a current voltage converter circuit.
An EEPROM which is of interest to this invention is disclosed in a paper entitled "A 55ns CMOS EEPROM" presented by R. Zeman et al. in the ISSCC held Feb. 23, 1984. The EEPROM disclosed in this paper includes memory cells arranged in pairs and each pair of cells are designed to be programmed to opposite state. The signals from the cell pair are differentially amplified by a suitable circuit. With this arrangement, storing one bit of data requires a memory cell area twice as large as in a conventional EEPROM.
Another memory device structure which is of interest to this invention is set forth in a paper entitled "An 80ns Address-Data Multiples 1Mb CMOS EPROM" presented by M. Yoshida et al. in the ISSCC held on Feb. 25, 1987. The disclosed EPROM does include a sense amplifier similar to that showing in FIG. 3 but does not include a circuitry for providing the reference voltage.